Freescale Semiconductor /MKE14Z7 /PDB0 /CH0C1

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Interpret as CH0C1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)EN0 (0)TOS0 (0)BB

TOS=0, EN=0, BB=0

Description

Channel n Control register 1

Fields

EN

PDB Channel Pre-Trigger Enable

0 (0): PDB channel’s corresponding pre-trigger disabled.

1 (1): PDB channel’s corresponding pre-trigger enabled.

TOS

PDB Channel Pre-Trigger Output Select

0 (0): PDB channel’s corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.

1 (1): PDB channel’s corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.

BB

PDB Channel Pre-Trigger Back-to-Back Operation Enable

0 (0): PDB channel’s corresponding pre-trigger back-to-back operation disabled.

1 (1): PDB channel’s corresponding pre-trigger back-to-back operation enabled.

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